<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> Yeah. So what you want IMO is a series of always-enabled data processing blocks, then microcode/state machine that acts on their output.</p><p>So for example</p><p>HARDWARE BLOCK CONFIG<br />A) edge detect CH1<br />B) edge detect CH2<br />C) edge detect CH3<br />D) 8-bit shift register, clk=CH2 rising, data=CH3, reset=CH1 falling</p><p>STATES<br />1) on falling edge A: go to 2<br />2) on data available D: go to 3 if 0x41, else go to 1. On rising edge A, go to 1<br />3) on data available D: trigger if 0x42, else go to 1. On rising edge A, go to 1</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> that&#39;s actually more what I&#39;m thinking. Basically the modules are always looking at the data, it&#39;s just new parameters that get clocked in once the previous condition is met. I can&#39;t think of a trigger that doesn&#39;t need a sequential list of conditions (with commands across channels treated kinda like multi-threading)</p>

<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> but my vision is less of a CPU and more of a coarse grained dataflow architecture where you have different modules analyzing the data in parallel, then outputs that feed into some kind of decision block</p>

<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> Well that&#39;s the idea. you build the blocks then the microcode wires them together into a specific protocol.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> I wouldn&#39;t want to hard code any protocols. I&#39;m trying to find the core modules that everything is built on and make those into atomic instructions. Then a compiler can take the current state of the scope (i.e. what is an ADC code in volts, what&#39;s a sample in time units) as well as a description of the desired protocol, and spit these instructions out.</p>

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<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> My vision a while back was a series of series of edge detectors feeding into serial/parallel pattern matching blocks, then a state machine acting on the output.</p><p>So you could have it look for &quot;falling edge on CH1&quot; then &quot;0x41 serially on CH2 data clocked by CH3 rising edge&quot; then &quot;0x20 serially on same pins&quot;, with a rising edge on CH1 or a mismatch of either byte clearing the state machine back to the start.</p><p>This would give you a SPI pattern match. I&#39;m sure you can see the potential to implement I2C etc. on the same logic block.</p>

<p><span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> <span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> Yup! It would have edge modules, slope and delay timers. Basically you feed it code (a list of conditions really) and the PC increments every time a condition is met. Here&#39;s a napkin sketch:</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@wingo" class="u-url mention">@<span>wingo</span></a></span> I designed several CPUs and build debug tooling for CPUs for both software _and_ RTL side and I still somewhat struggled with this!</p>