<p><span class="h-card" translate="no"><a href="https://mastodon.social/@mcc" class="u-url mention">@<span>mcc</span></a></span> Wasm does not have basic blocks. (block) is structured control flow: think {...} in C, and there&#39;s no `goto`</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> by the way, the block example, Katelyn G was saying there&#39;s some sort of unusual limitation on which basic blocks may follow each other, is there anything that stops me from br&#39;ing between blocks?</p>

<p><span class="h-card" translate="no"><a href="https://hachyderm.io/@recursive" class="u-url mention">@<span>recursive</span></a></span> &gt; The term is based on the multipurpose filling paste brand Polyfilla, a paste used to cover up cracks and holes in walls, and the meaning &quot;fill in holes (in functionality) in many (poly-) ways.&quot;</p><p>somehow this is exactly what i expected it to mean, despite no prior exposure</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://infosec.exchange/@sycophantic" class="u-url mention">@<span>sycophantic</span></a></span> right, that&#39;s exactly how I implemented it already</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://infosec.exchange/@sycophantic" class="u-url mention">@<span>sycophantic</span></a></span> My own implementation looks for I think at least one 55 as a state machine trigger followed by a D5 and then goes to frame content. Do not count the 55s, some PHYs/protocols can remove some of them (e.g. 10baseT before bit sync is achieved)</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://infosec.exchange/@sycophantic" class="u-url mention">@<span>sycophantic</span></a></span> so while I have your attention: in my Ethernet deframer (connected to output of PHY), how should I treat the preamble? do I just sync on the SFD and ignore all 55&#39;s before it? do I count the 55&#39;s?</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://hachyderm.io/@unlambda" class="u-url mention">@<span>unlambda</span></a></span> honestly, just using SystemVerilog at all is a sign of masochism so extreme, I cannot condone it (and I&#39;m into some pretty wild kinks)</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://hachyderm.io/@unlambda" class="u-url mention">@<span>unlambda</span></a></span> (yes i implemented a pcapng parser in systemverilog, call me crazy but i&#39;d rather do that than use python)</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://hachyderm.io/@unlambda" class="u-url mention">@<span>unlambda</span></a></span> Ah, OK.</p><p>I have the opposite (replay pcapng as frames over axi4-stream) for switch fabric debugging but currently no pcap sink</p>