Whole-known-network
<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> Well that's the idea. you build the blocks then the microcode wires them together into a specific protocol.</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> I wouldn't want to hard code any protocols. I'm trying to find the core modules that everything is built on and make those into atomic instructions. Then a compiler can take the current state of the scope (i.e. what is an ADC code in volts, what's a sample in time units) as well as a description of the desired protocol, and spit these instructions out.</p>
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<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> My vision a while back was a series of series of edge detectors feeding into serial/parallel pattern matching blocks, then a state machine acting on the output.</p><p>So you could have it look for "falling edge on CH1" then "0x41 serially on CH2 data clocked by CH3 rising edge" then "0x20 serially on same pins", with a rising edge on CH1 or a mismatch of either byte clearing the state machine back to the start.</p><p>This would give you a SPI pattern match. I'm sure you can see the potential to implement I2C etc. on the same logic block.</p>
<p><span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> <span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> Yup! It would have edge modules, slope and delay timers. Basically you feed it code (a list of conditions really) and the PC increments every time a condition is met. Here's a napkin sketch:</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@wingo" class="u-url mention">@<span>wingo</span></a></span> I designed several CPUs and build debug tooling for CPUs for both software _and_ RTL side and I still somewhat struggled with this!</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> lol. lmao</p>
<p>one more upsetting comment for the upsetting comment pile</p>
<p>Read my writeup. If you like the colour red or reactions involving the carbonyl atoms. Or for any other reasons</p><p><a href="https://isopropyletherperoxide.github.io/2025/05/02/Pyrylium.html" target="_blank" rel="nofollow noopener" translate="no"><span class="invisible">https://</span><span class="ellipsis">isopropyletherperoxide.github.</span><span class="invisible">io/2025/05/02/Pyrylium.html</span></a></p>
