Whole-known-network
<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> What I don't know is what the cleanest programming model for an end user developing triggers for this is going to look like.</p>
<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> Lol.</p><p>A VLIW processor may actually end up being the logical implementation of this. Who knows.</p><p>But the more I think about it, the more I lean towards a two-part system with a bunch of parallel function blocks that output one or more bits every cycle (each block having a bunch of config registers to specify muxing and thresholds and such), then a serial state machine operating on their output.</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> guess we doin HDL now. Once I finish these damn boards</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> I joked about it being a quasi CPU and it is quickly becoming straight up a CPU, I love it</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> Exactly what I was getting at. It's solvable, but not trivial.</p><p>You'll probably need multiple replicated copies of the logic and some speculation or replication to handle multiple cases in parallel then figure out what happened the next cycle or something.</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> you would unroll the state machine N times and pipeline, I think</p>
<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@kev" class="u-url mention">@<span>kev</span></a></span> Wow, that's a stunner!</p>
<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> No, you're missing the point.</p><p>Because you're running on the output of the 8:1 serdes, your trigger logic is at 125 MHz. But the *input* can still toggle faster than that (remember the frontend BW is what. 300+ MHz?)</p><p>So you need to consider what happens if you have >1 toggle in that 8-bit stream of samples. You may need to advance more than one state in a single clock cycle.</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> it will never clock at 1 GHz because we'd be doing this on the output of the 8:1 serdes. Just need a very simple module to track where exactly the sample was and then spit it back out another 8:1 serdes to the trigger output (that way it should be a fixed 8 cycle delay plus hardware delays)</p>