<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> I hope against hope, that this will make government institutions (European ones in particular) realise the importance of independent computing</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@gamingonlinux" class="u-url mention">@<span>gamingonlinux</span></a></span> mannn I&#39;m halfway through the first one. Amazing game</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> On interesting! I did find a bug in their clock gating cells where they used a non-blocking assignment instead of a blocking one too</p><p>Though that one i&#39;m a bit less sure is actually wrong but it does make my post netlist simulation agree with the pre synthesis sim 🤷</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@thezoq2" class="u-url mention">@<span>thezoq2</span></a></span> there is actually a legitimate reason to do it! it&#39;s clock dividers. if you use a non-blocking assignment there you&#39;ll introduce a time-0 race condition unless you rebalance the other branches of the clock tree too</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> Yeah, I thought I was dealing with that as well at first, but the simulation models (more like emulation models) I was using are extremely simple the DFF is just `always @(posedge clk) Q=D`</p><p>And using blocking assignment like that is just flat out wrong as far as I can tell</p>

<p><span class="h-card" translate="no"><a href="https://discuss.systems/@palvaro" class="u-url mention">@<span>palvaro</span></a></span> he missed the correct time to resign, but he can still resign in shame after the fact for what he did. a boy can dream</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> Excellent question! I don&#39;t even know why I rant about these things on linkedin of all places :D</p><p>If nothing else, it is fun to read the clueless replies :D</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@thezoq2" class="u-url mention">@<span>thezoq2</span></a></span> on careful re-reading: Verilator does not actually implement the Verilog simulation semantics, does it? if you don&#39;t expect the models to work in synthesis you should not expect them to work in Verilator either, I think</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@thezoq2" class="u-url mention">@<span>thezoq2</span></a></span> why would I want this</p>