<p>semiconductor manufacturing girl bath water (ultrapure, ASTM Type I, ISO 3696 Grade 1)</p>

<p>There once was a girl from Purdue<br />Who kept a young cat in a pew<br />She taught it to speak<br />Alphabetical Greek<br />But it never got farther than μ.</p>

<p><span class="h-card" translate="no"><a href="https://defcon.social/@moldavia" class="u-url mention">@<span>moldavia</span></a></span> just use Prism 👍</p>

<p>one of the problems is that when it starts toggling, sometimes it toggles as 01 for the nibbles at the tail of the packet, and sometimes it toggles as 10. the spec seems to imply you&#39;re supposed to be able to tell whether any given REF_CLK cycle (after initial assertion( carries CRS or DV, but it also defines the signal in a way where AFAICT this is simply not possible</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> unfortunately RMII is what you have to do if you want 10BASE-T1S</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> yes that&#39;s why RGMII was the first one i implemented</p>

<p>so far i&#39;ve spent like a week doing basically nothing but trying to implement the MAC side circuitry for CRS_DV and while i have a partially functional MAC i&#39;m not convinced i&#39;m any closer to fully understanding how this is supposed to happen</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> (RGMII appears to be sane with clock edge referenced DDR signals for everything)</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> I use SGMII and RGMII so no idea :)</p>