Whole-known-network
#cat [source](https://www.youtube.com/watch?v=snD9QSRNk4I)
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> I put the ROM into Ghidra, and now I cannot understand how this device could be put into download mode at all, although such a mode looks exist...<br />(BTW the PSR F50 service manual I got says a reserved MIDI port is also used for "ROM update")</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> okay looks good. Remembered when I was still in high school, got some quite old ARM7TDMI books in school library, and read...</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> I wonder whether the branch target is in flash or in int. ROM, because they seems to be not changeable, assume it's part of ROM?</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> It seems that no so official ARMv4 document exist now... This is from an appendix chapter named "ARMv4 and ARMv5 Differences" in ARMv7 manual, which should, be usable now?</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention" rel="nofollow noopener noreferrer" target="_blank">@<span>whitequark</span></a></span> good to know, will checkem out</p><p>but also good god do i need to not be wearing 12 latency-sensitive ESP32s (+ an ANT+ HR monitor) fr zhat, i have soooo much ambient 2.4G airspace contention already</p>
<p><span class="h-card" translate="no"><a href="https://nightcord.de/@icenowy" class="u-url mention">@<span>icenowy</span></a></span> that says ARMv7-A...</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> My memory of ARM shows that the ARM interrupt vector is either located at 0x00000000 or 0xffff0000 (called HIVECS), when without some late extensions. Seems that <a href="https://developer.arm.com/documentation/ddi0406/cb/Appendixes/ARMv4-and-ARMv5-Differences/System-level-register-support/The-exception-model" target="_blank" rel="nofollow noopener noreferrer" translate="no"><span class="invisible">https://</span><span class="ellipsis">developer.arm.com/documentatio</span><span class="invisible">n/ddi0406/cb/Appendixes/ARMv4-and-ARMv5-Differences/System-level-register-support/The-exception-model</span></a> is describing the vector on ARMv4/5.</p>
<p><span class="h-card" translate="no"><a href="https://floofy.tech/@qualia" class="u-url mention">@<span>qualia</span></a></span> yeah i use a 2.4G headset (arctis 1 wireless) and it's nice and low latency</p><p>no encryption afaik</p>