<p><span class="h-card" translate="no"><a href="https://hachyderm.io/@nrc" class="u-url mention">@<span>nrc</span></a></span> you can take a look at Rubocop or mbj&#39;s Unparser to see how they use it</p><p>apparently my AST format became somewhat of a de facto standard in the decade since, which is wild.</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> Same, I&#39;ve tried and failed to create metastabilty or at least something I could say for certain was. Perhaps the ~18 ps resolution on 7-series MMCM fine phase shift wasn&#39;t enough. I&#39;d have thought jitter would have taken care of the rest. Maybe my clock was too low and the metastability resolved before the 2nd stage FFs could sample it.</p><p>I should try it again with a DDS (~fs res.), like 700 MHz clocks.</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> CDC checks won&#39;t help if the input is coming from off chip and inherently async.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> we really need to add a built-in CDC checker to Amaranth...</p>

<p><span class="h-card" translate="no"><a href="https://hachyderm.io/@nrc" class="u-url mention">@<span>nrc</span></a></span> in my Ruby parser (which was afaik the first tooling grade parser for Ruby) i stored just the locations, and some tokens like commas required reparsing<br />a very small % of nodes had implied concrete information, most were abstract + locations </p><p>this was perfectly fine for refactoring and such</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> I wrote this uart core on an xc3s50a as one of my first FPGA projects ever.</p><p>Kept on using it for years afterward and always just assumed that my random data drops were EMI or signal integrity problems or something l.</p><p>Then one day I took a closer look at my RTL from 2010 and realized what was happening.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> oh, that&#39;s really cool</p><p>I&#39;ve never caught metastability in the wild, and I&#39;ve even tried to cause it on purpose</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> And adding a 2-flop sync between the rx pin and the existing uart core completely eliminated the problem.</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> Because I was getting failure states that were logically impossible and could only be explained by a flop being both high and low while sampled by other logic.</p>