@whitequark@mastodon.social FWIW for simple equivalence checking without any temporal elements it should be fairly easy to check it with SAT, and most SAT solvers can output a proof for the result (which can get subsequently checked by one of formally verified proof checkers) Though that's a fair bit of work for little benefit (I guess maybe it could be somewhat faster as well)

<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> enjoy, i pushed the latest changes <a href="https://github.com/prjunnamed/prjunnamed" target="_blank" rel="nofollow noopener" translate="no"><span class="invisible">https://</span><span class="ellipsis">github.com/prjunnamed/prjunnam</span><span class="invisible">ed</span></a></p><p>the whole thing is quite undocumented but this amaranth fork can output the IR <a href="https://github.com/prjunnamed/amaranth" target="_blank" rel="nofollow noopener" translate="no"><span class="invisible">https://</span><span class="">github.com/prjunnamed/amaranth</span><span class="invisible"></span></a></p>

<p>achievement unlocked: synthesize an entire 16-bit CPU while performing logical equivalence checking (combinational and sequential) for every transformation the compiler does, thus proving it correct (modulo correctness of the SMT solver and the IR-to-SMT translation code)</p>

<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> i just synthesized an entire (small, 16-bit) CPU while verifying every single transformation, both combinational and sequential</p>

<p>i&#39;ve added a basic sequential verification capability to it, too</p>

<p>Can I offer you a nice Orb in this trying time?</p>

<p>the way we ended up with a &quot;staging area&quot; was actually because it&#39;s written in Rust and lifetimes weren&#39;t working out without it, but as we continued working with this design it became clear that it&#39;s a key invention that&#39;s going to be really helpful</p><p>looks like LLVM is getting something similar, in concept if not in implementation <a href="https://discourse.llvm.org/t/rfc-sandbox-vectorizer-an-experimental-modular-vectorizer/79059" target="_blank" rel="nofollow noopener" translate="no"><span class="invisible">https://</span><span class="ellipsis">discourse.llvm.org/t/rfc-sandb</span><span class="invisible">ox-vectorizer-an-experimental-modular-vectorizer/79059</span></a></p>

<p><span class="h-card" translate="no"><a href="https://social.sciences.re/@MonniauxD" class="u-url mention">@<span>MonniauxD</span></a></span> I do hardware compilation, yes!</p><p>I don&#39;t currently have a functioning reducer tool but I will absolutely do it the moment I get a testcase that&#39;s too annoying to reduce by hand; the IR is well suited for it</p><p>you can think of what I&#39;m working on as a funciton with a single basic block and no phis. the reality is more complex than that but that&#39;s the general feeling of working with the IR</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> awesome!</p>