Whole-known-network
<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> there is no fundamental difference between word-level and bit-level cells and the entire flow is hybrid, only lowering to bit-level when necessary</p><p>there is just one netlist representation / stage / etc, it is used for the entire flow after the frontend (and will be used for post-place/route checkpoints too)</p>
<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> right now prjunnamed does:</p><p>- ingestion of UIR netlists with decision trees (basically Yosys processes), or else Yosys JSON<br />- simplification of combinational and sequential expressions, FF control inference<br />- merging of equivalent cells (think GVN)<br />- splitting of coarse cells with partially unused outputs<br />- lowering of arithmetics (except adders), shifts, multipliers, etc into simpler logic<br />- lowering of memories into FF+MUX<br />- if requested, LUT/FF synthesis for iCE40</p>
<p><span class="h-card" translate="no"><a href="https://not.acu.lt/@ignaloidas" class="u-url mention">@<span>ignaloidas</span></a></span> yeah pretty much!</p>
<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> we don't do P&R yet, this is just target-dependent synthesis. if you use it with Amaranth you don't need Yosys at all, otherwise you'd need it to ingest Verilog and there's an intricate Yosys script you'll need for that</p><p>we do aim to do P&R also, but the 400 ms figure is very much only synthesis</p>
<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> prjunnamed is very much not ready for circuits of that size (biggset one i regularly test on is 5k LUTs, for context; 2 seconds for iCE40 synthesis) and there's multiple known sources of inefficiency, but we also do aim to be able to process UltraScale-sized designs eventually</p><p>we started writing code on, um, Jan 23 of this year</p>
@whitequark@mastodon.social I'd say it's a path to formally verified optimization - but that has zero benefits until there's formal verification for the rest of compilation
<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> LUT synthesis quality isn't as good as abc's `&if` but we're getting there; optimization quality is at least as good as Yosys at a fraction of the runtime</p>
<p><span class="h-card" translate="no"><a href="https://not.acu.lt/@ignaloidas" class="u-url mention">@<span>ignaloidas</span></a></span> while i could indeed do this i can't think of what problem i have that it will solve; the main thing i built this for is because i'm building a new toolchain from scratch and we have to test it, like, somehow. and i'm not in a mood to simulate netlists</p>
<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> yes. if you turn them off synthesis finishes in uh. 200 milliseconds</p>