<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> I mean I wrote all of my thesis code in v2005 because I still had a lot of Spartan-6s in the test board farm and ISE was, well, ISE.</p><p>But yeah, early vivado was missing a lot of SV features that I now use heavily. Interfaces make e.g. AMBA buses so much less painful to use. My somewhat cynical opinion is that the ip integrator exists in large part because SV support wasn&#39;t up to the point of enabling one-liner AXI connections between modules.</p><p>So rather than fixing their frontend they created a giant bloated pile of XML and slow tcl+java based code generation.</p>

<p><span class="h-card" translate="no"><a href="https://chaos.social/@weirdunits" class="u-url mention">@<span>weirdunits</span></a></span> thicc</p>

<p><span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> basically constraints need to be applied to the net or to the driver pin (there are various ways you can do this) but a lot of vendors end up applying them to the net name, which aren&#39;t in general preserved unless you (*keep*). this is very silly</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> oh, yeah, I forgot that it had a weirdly lagging SV support for quite a while</p><p>I suppose this wouldn&#39;t really fly today, though who knows</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> neat! also ouch on the optimising out of constraints, especially if they&#39;re explicit. that&#39;s just silly lol</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> FWIW vivado gained support for arrays of interfaces late enough in the game that I had to do a major ASIC project using a bunch of structs instead of interfaces, where interfaces would have been a better fit.</p><p>DC was fine with interfaces at the time, but we needed to be able to synthesize the RTL for U+ to prototype so anything Vivado didn&#39;t support was off limits.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> in the immediate future the plan for verilog frontend is &quot;use yosys&quot; which as we both know is incredibly underwhelming from just about perspective; this is basically just to make sure we can get enough test netlists to get to the point it makes sense to prioritize a better frontend</p>

<p><span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> vivado, for all its flaws, gets a shocking amount of these things right, and it&#39;s actually been nice to think about implementing all those features but in a modern open source implementation</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> that is table stakes for a production grade FPGA toolchain, yes</p>