Whole-known-network
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> anyway, my concept for building fast MCU/etc dumpers is that i want you to be able to describe an algorithm in a Python-based set of instructions (you could call it a DSL but it's really just a series of commands) that gets transformed into a command stream for the FPGA. you know, sort of like GPU command buffers</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> what scares me though is ADIv5.2 with complex stuff like multidrop SWD. it's just really expansive and i'm like one girl</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> i have an unfinished branch. there are a few things in the core architecture that i want to improve that i had to make a detour into building Amaranth infra for first (streams in particular, they're basically AXI-Stream compatible)</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> Do you have hardware ADIv5 support for fast dumping of modern MCUs?</p>
<p><span class="h-card" translate="no"><a href="https://with.iridium.ink/@artemis" class="u-url mention">@<span>artemis</span></a></span> nicenice</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> the macrocell is soo much simpler than ADIv5 that i definitely _could_ implement dumping at, idk, 1 MB/s i think if i tried? i guess i implemented MIPS EJTAG and this isn't even worse</p><p>i don't wanna deal with stuff like FIQ banking though</p>
<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> Yeah I've never worked with any ARM stuff that predated ADIv5 or ARMv6/v7-M.</p><p>All of the ARM9 stuff etc I completely sidestepped... went from 8-bit PICs with custom CPU/debug to PIC32 MIPS M4K with standard EJTAG to STM32 with modern ARM debug.</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> remote_bitbang makes it even slower than usual, but also openocd's architecture is kind of fundamentally incredibly slow? if i was using a "real" JTAG probe (i mean some FTDI crap for example) it would still be capped at maybe 20 KB/s. i'm sure you know</p><p>i have actually considered implementing the debugging algo but this core is so ancient i'm not sure this is worth the effort</p>
<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> because it's not a flash; it's using openocd remote jtag since i never implemented native algorithms for uhhh.... Embedded ICE v1 that ARM720T is using</p>