<p><span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> Also LSB-first bit ordering is an abomination. I hate how networking serdes people seem to have standardized on it.</p><p>First thing all of my Ethernet IPs working with Xilinx SERDES do is flip the bit ordering around so 8&#39;h80 is serialized as 1-0-0-0-0-0-0-0.</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> I do agree mode 3 will cover the vast majority of parts.</p><p>I&#39;ve looked through a handful of datasheets of parts I use and MAX2871 is the only one I expect to be problematic as I recall it not working with anything not matching what&#39;s shown in the timing diagram.</p><p>I&#39;m currently procrastinating on writing some gateware for a SPI bus with an LSB first abomination from Psemi and a 6 bit part from Hittite. Analog designers aren&#39;t great at digital interfaces.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> this of course comes on the back of having a robust methodology for building high-performance peripherals; if you want something custom, you copy the upstream SPI peripheral into your codebase, modify it as you wish, and keep it yours</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> the reason boils down to &quot;why should everybody else spend verification effort on your weird chip if they work on the SPI gateware upstream? what is the benefit of this to the community? the burden is clear&quot;</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> hm, hearing this makes me conclude that if you want weird things like LSB-first transfers or strobing CS as end-of-byte you should just not use amaranth-stdio SPI gateware at all</p><p>for context, the *Q*SPI gateware is going to be strictly mode 3 no matter what since that&#39;s what all flashes support; any configurability whatsoever would be restricted to SPI gateware only, and I&#39;m trying to see how much of it I even want to have</p><p>mode 0 is maybe within scope, other stuff def not</p>

@thendrix@social.hendrixgames.com @disarray@layer02.net @limepot@ouroboros.gay all of these questionnaires are

@vaartis@pl.kotobank.ch @disarray@layer02.net @limepot@ouroboros.gay that part of the quiz is just stupid because apart from one or two questions it’s all statistics

@limepot@ouroboros.gay @disarray@layer02.net right, i guess i really am bad at understanding things, the next question i knew words from neither column besides ROFL, GR8 and YOLO but nobody fucking says words from neither column in actuality

@disarray@layer02.net @limepot@ouroboros.gay what is the question here??