<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> sure, i mean two async clocks from two PLLs</p>

<p>I&#39;m confused by unclear web sites …</p><p>Anyone out there have experience running Carbon apps (Mojave, currently in a Parallels VM) on Apple Silicon Macs? Is there an Apple Silicon version of Parallels that will emulate an Intel CPU? Can I run Intel Parallels in Rosetta to achieve that?</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> I haven&#39;t trusted FPGA RNGs since I ran a test a while back of on die ring oscillators and found them injection locking to each other through power rails.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> dunno, i would race two async clocks against each other</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> i thought vivado didn&#39;t exist in 2013 and had to look it up... apparently it did huh</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <br />Oh yeah</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> The whole reason I&#39;m doing this is to lay groundwork for future projects like my Ethernet switch.</p><p>Implementing a SSH server on an FPGA or a softcore sounds like a nightmare (in particular without a hard TRNG IP you can use for session key generation).</p><p>I absolutely don&#39;t need this much bandwidth between the MCU and FPGA for that project, but optimization is fun. If you&#39;re not counting clock cycles and instructions, are you even enjoying your day?</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> I mean, my goal here is mostly to maximize the MCU-FPGA bandwidth. No matter how I partition the workload, improved performance of the link is better all around.</p><p>And hey, at least I didn&#39;t use a Zynq.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> I do yeah!</p><p>needless to say i&#39;m team all-on-FPGA, your MCU suffering for weeks really drives the point in</p>