<p><span class="h-card" translate="no"><a href="https://hachyderm.io/@nrc" class="u-url mention">@<span>nrc</span></a></span> in my Ruby parser (which was afaik the first tooling grade parser for Ruby) i stored just the locations, and some tokens like commas required reparsing<br />a very small % of nodes had implied concrete information, most were abstract + locations </p><p>this was perfectly fine for refactoring and such</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> I wrote this uart core on an xc3s50a as one of my first FPGA projects ever.</p><p>Kept on using it for years afterward and always just assumed that my random data drops were EMI or signal integrity problems or something l.</p><p>Then one day I took a closer look at my RTL from 2010 and realized what was happening.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> oh, that&#39;s really cool</p><p>I&#39;ve never caught metastability in the wild, and I&#39;ve even tried to cause it on purpose</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> And adding a 2-flop sync between the rx pin and the existing uart core completely eliminated the problem.</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> Because I was getting failure states that were logically impossible and could only be explained by a flop being both high and low while sampled by other logic.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> i def should build a design for this and then try and break it</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> how did you know it&#39;s metastability specifically and not just jitter resulting in capturing the wrong thing sometimes (i.e. a normal race)?</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> Fair enough.</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> Yeah modern nodes have very short windows which makes catching metastability related bugs tricky.</p><p>~5 years ago I caught one in a UART core I had been using for quite a long time that would occasionally drop a byte when I was sending a lot of data. Turns out I wasn&#39;t synchronizing the input properly (i.e. at all).</p>