<p>Fixed the transmit buffer gateware to clear the unused low bytes, but we&#39;re still seeing the extra 0x06fc at the end of the frame for some reason, which borks the CRC.</p><p>The frame leaving the transmit CDC FIFO (in the SERDES clock domain) looks correct.</p>

"the body is a temple!" this body is not a place of honor. no highly esteemed deed is commemorated here. nothing is valued here. what is here is dangerous and repulsive.

@arcana@layer02.net @sun@shitposter.world very strange that it is not working.

stopping SPC for the night, see you in eight hours.

I discovered a nigerian internet forum in english and I'm having the time of my life. I think I need to sign up

i wish i could be happy

@Mitsu@outerheaven.club preggers

<p><span class="h-card" translate="no"><a href="https://mastodon.social/@film_girl" class="u-url mention">@<span>film_girl</span></a></span> i was desperate for a gmail invite so i bought a couple on eBay.</p>

<p>The frame captured on the FPGA entering the transmit FIFO from the management/QSPI bus clock domain (i.e. data sent by the microcontroller to the FPGA) looks valid. </p><p>But looking closely we can see we sent 0x06fc0a02 with 2 valid bytes on the bus at the end of the frame. Those extra two invalid bytes should be ignored by the MAC but apparently weren&#39;t? Should be easy enough to mask off, but that doesn&#39;t explain where the extra 06fc at the end of the frame came from.</p>