<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> I vaguely recall you talking about it before but I can&#39;t remember the details.</p>

<p><span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> Yeah.</p><p>I mean, I&#39;m not paying MSRP though... You&#39;ve heard about how I ended up getting a good deal right?</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> ah, cool, thanks. I did wonder if it was a simulation thing. I&#39;ve still not managed to get my head around EM sims, I&#39;m hoping to get time to follow along with niconiconi&#39;s guide before too long (although I can&#39;t say I&#39;m looking forward to battling FreeCAD). shame Sonnet is just insanely pricey.</p>

<p><span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> Feedlines for the simulator, they&#39;re de-embedded but have to be present to make the ports work out.</p><p>Tl;dr you get weird results if you try to make a port that doesn&#39;t have ground on an adjacent layer to use as a reference. This is fine if you have a reference plane but if you&#39;re voiding the plane, adding a short feedline seems to usually be the easiest way to work around it.</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> nice. I just noticed the trace seems to be on both sides of the pad - what&#39;s the deal with that?</p>

<p><span class="h-card" translate="no"><a href="https://chaos.social/@gsuberland" class="u-url mention">@<span>gsuberland</span></a></span> Yep.</p><p>This is the host-side launch for the connector that will be going from the FPGA board to the two line cards (two connectors, total twelve 5 Gbps NRZ lanes, per line card) as well as to the front panel dual SFP28 carrier (one connector, total four 25 Gbps NRZ lanes).</p>

<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> nice! I assume you&#39;re targeting Zdiff=100Ω on this?</p>

<p>I&#39;m pretty happy with the top side Samtec ARF6 launch simulations now.</p><p>S11:<br />* Red: No cutout, -12 dB at 10 GHz, -7 at 20 GHz, -4.8 at 30 GHz<br />* Blue: Rectangular ground cutout the size of the pad, -22.5 at 10 GHz, -16.4 at 20 GHz, -11.7 at 30 GHz<br />* Green: 30um larger than the pad on all sides (1.06 x 0.41 mm), -30.5 at 10 GHz, -22 at 20, -15 at 30.</p><p>With the oversized cutout it&#39;s more than good enough for QSGMII and 25Gbase-R.</p><p>TDR:<br />* Red: No cutout, 64Ω Zdiff at the launch<br />* Yellow: Pad-sized cutout, 86Ω<br />* Orange: Oversized cutout, 94Ω</p>

<p>My new marketing pitch and the summary of my <a href="https://io.mwl.io/tags/writing" class="mention hashtag" rel="tag">#<span>writing</span></a> career:</p>