<p>I just described bus timetables at a local transit center as &quot;leading / lagging the ferry phase&quot; in order to &quot;provide sufficient setup/hold margin&quot; for transfers between modes of transit.</p><p>Does that make me some kind of nerd?</p><p>It seriously is a synchronous CDC between, dare I say, buses.</p>

@whitequark@mastodon.social @rygorous@mastodon.gamedev.place (the plus side of it being a 1T 8051 of course is that a uart interrupt probably only costs like 10 cycles, so it doesn't matter _that_ much. but probably what I should do is just max out the BRG at like 3mbaud and hook it up to my Glasgow)

@whitequark@mastodon.social @rygorous@mastodon.gamedev.place What's this DMA you speak of? *Laughs in 8051*

<p><span class="h-card" translate="no"><a href="https://hachyderm.io/@skinnylatte" class="u-url mention">@<span>skinnylatte</span></a></span> corollary: emigration is a lot easier if a place already hates you and you have zero friends there (i&#39;ve done this twice. can&#39;t recommend)</p>

<p><span class="h-card" translate="no"><a href="https://mastodon.gamedev.place/@rygorous" class="u-url mention">@<span>rygorous</span></a></span> <span class="h-card" translate="no"><a href="https://akko.erincandescent.net/users/erincandescent" class="u-url mention">@<span>erincandescent</span></a></span> i think the embedded UARTs often don&#39;t have FIFOs, like for example stm32f103 just doesn&#39;t, you&#39;re supposed to use DMA</p>

<p><span class="h-card" translate="no"><a href="https://akko.erincandescent.net/users/erincandescent" class="u-url mention">@<span>erincandescent</span></a></span> I mean the usual FIFO for UARTs is like 16 bytes so it&#39;s still a considerable interrupt volume too.</p><p>This is not gonna make things faster in terms of bytes written because you&#39;re clearly actually limited by serial BW but you _should_ be able to turn this into a situation where you have some double-digit % of time in ISRs and turn a lot of your busy wait for UART into idle time instead</p>

@rygorous@mastodon.gamedev.place busy waiting but it probably wouldn't have helped to put a fifo in front because the log volume would very quickly have swamped the buffer (I was logging every byte received in hex and my laptop was impatiently spammig _a lot_ of messages at me)

<p><span class="h-card" translate="no"><a href="https://akko.erincandescent.net/users/erincandescent" class="u-url mention">@<span>erincandescent</span></a></span> in that case, go ham on the protocol stack, obvs</p><p>For reals though, are we talking busy waiting for the UART or is this a &quot;FIFO-in-front-and-interrupts&quot; kind of situation?</p>

@rygorous@mastodon.gamedev.place no