<p>by the way, the "bizarre, seemingly impossible way" is that the CPU can execute an `STM r0, {r0-r15}` command just fine, but when asked to do `MSR CPSR_c, 0xc0` it just... doesn't switch the mode</p><p>the MSR opcode is a single word. there's nothing in how it's executed that isn't already tested by the preceding and succeeding STM opcode. it doesn't touch system memory or anything; it's one of the simplest commands you can imagine. the data transferred by STM is always right</p><p>it's just... broken</p>
