<p><span class="h-card" translate="no"><a href="https://pony.social/@thephd" class="u-url mention">@<span>thephd</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@mcc" class="u-url mention">@<span>mcc</span></a></span> Amaranth is a better language than Verilog because it is a _lower_ level language, without various kinds of poorly defined "inference" that in practice require the use of a "linter" to be sure of any semantics at all</p><p>it stays close to the netlist, while SystemVerilog doesn't even bother to define what the synthesizable (i.e. translatable to hardware) subset even _is_, every vendor decides on their own!!</p>
