<p><span class="h-card" translate="no"><a href="https://infosec.exchange/@david_chisnall" class="u-url mention">@<span>david_chisnall</span></a></span> <span class="h-card" translate="no"><a href="https://discuss.systems/@steve" class="u-url mention">@<span>steve</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@wingo" class="u-url mention">@<span>wingo</span></a></span> FPGA synthesis, actually</p><p>most of it is this straightforward term rewriting system; it runs on graphs rather than trees but otherwise the idea is the same</p><p><a href="https://github.com/prjunnamed/prjunnamed/blob/main/generic/src/simplify.rs" target="_blank" rel="nofollow noopener" translate="no"><span class="invisible">https://</span><span class="ellipsis">github.com/prjunnamed/prjunnam</span><span class="invisible">ed/blob/main/generic/src/simplify.rs</span></a></p><p>the fixpoint loop is here, it also runs the merge and split passes. these are not inherently required for the domain, but we use word-wide (multibit) terms in the netlist, so you end up missing simplifications if you never split off unused bits of the result, etc</p><p><a href="https://github.com/prjunnamed/prjunnamed/blob/main/generic/src/lib.rs" target="_blank" rel="nofollow noopener" translate="no"><span class="invisible">https://</span><span class="ellipsis">github.com/prjunnamed/prjunnam</span><span class="invisible">ed/blob/main/generic/src/lib.rs</span></a></p>