<p><span class="h-card" translate="no"><a href="https://mastodon.social/@thezoq2" class="u-url mention">@<span>thezoq2</span></a></span> on careful re-reading: Verilator does not actually implement the Verilog simulation semantics, does it? if you don't expect the models to work in synthesis you should not expect them to work in Verilator either, I think</p>
