<p><span class="h-card" translate="no"><a href="https://types.pl/@lenary" class="u-url mention">@<span>lenary</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@regehr" class="u-url mention">@<span>regehr</span></a></span> <span class="h-card" translate="no"><a href="https://hachyderm.io/@unlambda" class="u-url mention">@<span>unlambda</span></a></span> this is a synthesizer for an FPGA where we're using a really nice representation: a "coarse cells with fine wires" netlist</p><p>it is basically SSA with no flow control where each bit of each instruction gets globally numbered and used by other instructions. input/output (think args/return) are just instructions. wire names are also an instruction. there are no modules, metadata, or types</p><p>it's a pleasure to work on :D</p>
