<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> The other challenge will be how to handle higher speed serial-ish protocols that might change states quickly.</p><p>With 4-channel mode it's easy because you can run trigger logic at 250 MHz and have one set of updates per cycle.</p><p>But with 1-channel mode you can't clock the trigger logic at 1 GHz, so you have to consider what happens if you have more than one transition in the signal in a single clock cycle of the trigger state machine. This will only get worse as you transition to faster ADCs in the future and the number of ADC samples per FPGA clock grows.</p><p>I don't have all the answers, just pointing out design considerations.</p>
