<p><span class="h-card" translate="no"><a href="https://digipres.club/@abrasive" class="u-url mention">@<span>abrasive</span></a></span> <span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> So the high level concept is that the debug interface was bridging datagrams in the on-chip interconnect out to a TCP socket on the client PC.</p><p>Essentially each client (unit test, logic analyzer, etc) connected to the debug server would get a virtual device ID that it could use to send and receive packets to on-chip devices as if it were a very slow on-chip IP.</p><p>The bus words were all 32 bits wide so the natural implementation over JTAG would be a single 32-bit scan register that you'd hit over and over to send multiple words.</p><p>The problem is, this is slooow especially if you're using FTDI things that run over USB 2.0 with large bulk transfers etc.</p>
