<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> I wrote this uart core on an xc3s50a as one of my first FPGA projects ever.</p><p>Kept on using it for years afterward and always just assumed that my random data drops were EMI or signal integrity problems or something l.</p><p>Then one day I took a closer look at my RTL from 2010 and realized what was happening.</p>