<p>Ok so I think this is going to be the plan for the front panel:</p><p>* Main MCU accepts SFTP command, initializes SFTP server routine</p><p>* Main MCU sees a "write file" command for the front panel MCU's firmware file</p><p>* Main MCU sends SPI command to front panel MCU to reboot in DFU mode</p><p>* Main MCU parses incoming ELF as it comes in, finds data that needs to go to flash, and pushes it over SPI to front panel</p><p>* Final CRC verification, if this fails front panel remains in DFU mode</p><p>* Main MCU sends SPI command to front panel MCU to reboot in normal mode with new firmware</p><p>All of this has to be done "fire-and-forget" right now, since the SPI SO pin on the front panel MCU is unusable due to an errata (if I enable it, JTAG stops working and the chip soft-bricks). </p><p>I'm not sure if there's any way around this, perhaps by clever use of open drain signaling somewhere to signify "ready"? Otherwise I may have no choice but to run open-loop and just hard code conservative timeouts on the main MCU side.</p>
