<p>The frame captured on the FPGA entering the transmit FIFO from the management/QSPI bus clock domain (i.e. data sent by the microcontroller to the FPGA) looks valid. </p><p>But looking closely we can see we sent 0x06fc0a02 with 2 valid bytes on the bus at the end of the frame. Those extra two invalid bytes should be ignored by the MAC but apparently weren't? Should be easy enough to mask off, but that doesn't explain where the extra 06fc at the end of the frame came from.</p>
