<p>by the way, the &quot;bizarre, seemingly impossible way&quot; is that the CPU can execute an `STM r0, {r0-r15}` command just fine, but when asked to do `MSR CPSR_c, 0xc0` it just... doesn&#39;t switch the mode</p><p>the MSR opcode is a single word. there&#39;s nothing in how it&#39;s executed that isn&#39;t already tested by the preceding and succeeding STM opcode. it doesn&#39;t touch system memory or anything; it&#39;s one of the simplest commands you can imagine. the data transferred by STM is always right</p><p>it&#39;s just... broken</p>
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