<p><span class="h-card" translate="no"><a href="https://fosstodon.org/@aleksorsist" class="u-url mention">@<span>aleksorsist</span></a></span> <span class="h-card" translate="no"><a href="https://social.treehouse.systems/@urja" class="u-url mention">@<span>urja</span></a></span> My vision a while back was a series of series of edge detectors feeding into serial/parallel pattern matching blocks, then a state machine acting on the output.</p><p>So you could have it look for "falling edge on CH1" then "0x41 serially on CH2 data clocked by CH3 rising edge" then "0x20 serially on same pins", with a rising edge on CH1 or a mismatch of either byte clearing the state machine back to the start.</p><p>This would give you a SPI pattern match. I'm sure you can see the potential to implement I2C etc. on the same logic block.</p>
