<p><span class="h-card" translate="no"><a href="https://recurse.social/@jleigh" class="u-url mention">@<span>jleigh</span></a></span> ok so if you want to play with it you should join our channel via Matrix or IRC (they're bridged), but to start with Verilog you will want something like...</p><p>yosys *.v -p 'hierarchy -auto-top; proc -norom -noopt; flatten; memory_collect; select A:top; write_json netlist.json'</p><p>and it kind of gets worse from there if you want to instantiate target cells (you also need to read their prototypes or the JSON won't have port directions and everything will break)</p>
