<p><span class="h-card" translate="no"><a href="https://ioc.exchange/@azonenberg" class="u-url mention">@<span>azonenberg</span></a></span> <span class="h-card" translate="no"><a href="https://chaos.social/@dlharmon" class="u-url mention">@<span>dlharmon</span></a></span> hm, hearing this makes me conclude that if you want weird things like LSB-first transfers or strobing CS as end-of-byte you should just not use amaranth-stdio SPI gateware at all</p><p>for context, the *Q*SPI gateware is going to be strictly mode 3 no matter what since that's what all flashes support; any configurability whatsoever would be restricted to SPI gateware only, and I'm trying to see how much of it I even want to have</p><p>mode 0 is maybe within scope, other stuff def not</p>
