<p>imagine being able to set a breakpoint on a condition in your source code, and then run your simulation up until the point where the condition becomes true--all with as little as 10% time overhead and without multi-gigabyte VCD files, but while still retaining the full view of the design... anywhere in a mixed Amaranth/Verilog/VHDL environment</p><p>this was prototyped and should be ready for use with just a bit of development and polishing</p>