<p><span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention">@<span>whitequark</span></a></span> <span class="h-card" translate="no"><a href="https://types.pl/@wren6991" class="u-url mention">@<span>wren6991</span></a></span> Probably more than hyperram.</p><p>But 32 Gbps is closer to what you'd get from a full scale SSTL bus, e.g. a 32 bit DDR3 1066 interface is 34 Gbps of interface bandwidth.</p><p>I suspect the power consumption of a single SERDES would be pretty favorable compared to 32 SSTL DQ pins, four DQS lanes, plus the C/A bus, etc. And you're doing all that with a total of four signals. There's definitely a spot in the design space it would work well for.</p>
